RAM Speed and CPU Speed: How They're Related
How are RAM speed and CPU speed related?
RAM and CPU speed are related by cycle time and wait states.
Cycle Time
----------
Cycle time is the minimum time it takes the processor to "turn around," or
complete execution of an instruction.
On a 25 MHz CPU, the clock generates 25,000,000 pulses per second. That is to
say, each pulse comes every 1/25,000,000 second (or after 25,000,000 pulses,
one second has elapsed).
One divided by 25,000,000 means each pulse lasts 40 nanoseconds
(4.0 x 10 EE-8). So, if the processor were running at top speed, it could
write a value to RAM, change it in one cycle, and rewrite it 40 nanoseconds
later. In this system, the RAM would have to be able to respond within 40ns,
or 40ns RAM. However, 40ns RAM is hard to make and expensive, so someone had
the idea to let the processor go fast for everything else it does, but to
slow down accesses to RAM.
Wait State
----------
Thus was born the idea of the wait state, in which the processor spins its
wheels for one, two, or more cycles, to give the RAM a chance to catch up.
So in our mythical 25 MHz machine described above, one wait state would
mean we could use plentiful and cheap 80ns RAM. Two wait states would
permit 120ns RAM, and so on.
Some designs are easy, and use a fixed number of wait states -- but not the
Macintosh. Depending on what activity is being done and whatever else is
going on, the Macintosh can impose a variable number of wait states.
Generally, though, if you use the calculation above with recent designs, you
can assume one wait state and get the RAM speed.
(1 divided by clock speed) x 2 = ___ ns)
Wait states are not free, however. While the processor is spinning its
wheels, that fast CPU and support hardware you paid for is useless. For
this reason, cache RAM, which is very fast, can be used to eliminate or
reduce wait states to the processor, and then the cache controller is used
to write to slower main RAM. Also, though this refers to writes, the same
applies to reads.
Cycle Time
----------
Cycle time is the minimum time it takes the processor to "turn around," or
complete execution of an instruction.
On a 25 MHz CPU, the clock generates 25,000,000 pulses per second. That is to
say, each pulse comes every 1/25,000,000 second (or after 25,000,000 pulses,
one second has elapsed).
One divided by 25,000,000 means each pulse lasts 40 nanoseconds
(4.0 x 10 EE-8). So, if the processor were running at top speed, it could
write a value to RAM, change it in one cycle, and rewrite it 40 nanoseconds
later. In this system, the RAM would have to be able to respond within 40ns,
or 40ns RAM. However, 40ns RAM is hard to make and expensive, so someone had
the idea to let the processor go fast for everything else it does, but to
slow down accesses to RAM.
Wait State
----------
Thus was born the idea of the wait state, in which the processor spins its
wheels for one, two, or more cycles, to give the RAM a chance to catch up.
So in our mythical 25 MHz machine described above, one wait state would
mean we could use plentiful and cheap 80ns RAM. Two wait states would
permit 120ns RAM, and so on.
Some designs are easy, and use a fixed number of wait states -- but not the
Macintosh. Depending on what activity is being done and whatever else is
going on, the Macintosh can impose a variable number of wait states.
Generally, though, if you use the calculation above with recent designs, you
can assume one wait state and get the RAM speed.
(1 divided by clock speed) x 2 = ___ ns)
Wait states are not free, however. While the processor is spinning its
wheels, that fast CPU and support hardware you paid for is useless. For
this reason, cache RAM, which is very fast, can be used to eliminate or
reduce wait states to the processor, and then the cache controller is used
to write to slower main RAM. Also, though this refers to writes, the same
applies to reads.