Yes. This white paper was written by Steve Winegarden.
Stargate: PCI to NuBus Bridge ASIC
By Steve Winegarden
Power Computing Corporation
I. Introduction
The PCI to NuBus Bridge provides the data path and control functions to form a bridge from the PCI Local Bus to the NuBus. It will facilitate use of existing Power Macintosh compatible NuBus interface cards in conjunction with the new PCI Local Bus compatible Power Macintosh computers. It is implemented as a single chip and appears as a PCI-to-Foreign-Bus bridge device on PCI open firmware software provided on an EPROM which enables Stargate to operate in the MacOS environment using the standard slot manager interface.
A. Features
PCI 2.0 compliant 32-bit bus interface.
Direct PCI connection.
PCI bus master/slave timing referenced to PCI signal PCLK (33.3
Mhz max).
NuBus ANSI/IEEE Std 1196-1987 compliant 32-bit bus interface.
NuBus connection via buffers for full bus drive compliance.
Clock generation for NuBus and NuBus90 clocks based on 40 Mhz
reference.
5 Volt only operation.
PCI expansion ROM.
B. Outline
The NuBus handles only memory space references and interrupts.
1. From the PCI bus:
This bridge passes only memory references through to the NuBus.
Memory references will be passedthrough according to which
NuBus slot spaces are enabled. No other memory references will
be sent through. No references to either I/O space or PCI
configuration space will be passed through. References to the
configuration space of this bridge chip will be handled here. No
address translation or byte swapping will take place in
references from the PCI bus to the NuBus.
2. From the NuBus:
This bridge only generates memory references on the PCI bus.
References corresponding to slot space or super slot space will
not be sent through if the corresponding space is enabled on the
NuBus. No address translation or byte swapping will take place
in references from the NuBus to the PCI bus.
Interrupts when enabled are passed from the NuBus to the INTA#
line on the PCI bus.
The 20 Mhz clock for use in 2X block transfers as defined by the
Draft Standard for NuBus 90 is generated and an enable control
provided (/CLK2X, /CLK2XEN).
The following NuBus or NuBus 90 features are not implemented:
Parity (/SP, /SPV).
Cache coherency (/CBUSY, /CM2, /CM1, /CM0).
2X block transfer (/TM2).
Serial bus (/SB1, /SB0).
No previous Macintosh implemented any of these features.
The power fail warning signal from the NuBus is not handled by this
chip in any way (/PFW).
Reset on the PCI bus will cause the generation of a corresponding
reset on the NuBus and will clear all configuration control and
status bits.
The following block diagram shows the major functional blocks which
comprise this chip.
II. Architecture
A. Bridge Characteristics
+PCI Bus Commands are translated into NuBus Commands and visa
versa.
+Individual transactions are not merged into larger blocks.
+The cache line size can be set to 4, 8 or 16 words of 32 bits
each.
+The first series of machines will use 8 word cache lines.
+No read ahead is done from either bus.
+NuBus operations are always accepted and completed.
+PCI writes are posted.
+PCI reads are retried if the previous command has not yet
completed or if the bridge does not own the NuBus.
B. Data Flow
+All memory related commands that can be generated on the PCI
bus are accepted.
+The PCI slave accepts bursts up to two words unless a cache
line related command is indicated in which case it will handle
the entire cache line at once.
+The NuBus slave accepts all possible 1X block transfer sizes
(up to 16 words).
C. Clocks
+The PCI interface operates from the clock delivered on the PCI
Local Bus whose frequency is 33.3 Mhz.
+The NuBus interface generates the NuBus clocks from a 40Mhz
reference, four times the NuBus clock frequency.
+Other than the NuBus specification itself, therre are no
further specifications on this clock.
D. Services Expected Outside This Chip
1. PCI
The PCI Local Bus pullups, PCI Host, and PCI Arbitration
functions are provided by the host system.
2. NuBus
The NuBus pullups, termination, and high current buffering
functions are provided external to this chip. A reference clock
and EEROM if applicable are also provided external to this chip.
E. Data Buffers
1K bits: PCI Target and NuBus Master.
512 bits: NuBus Slave and PCI Master.
Dual Port Static RAM: 1-read and 1-write.
Address, data and controls multiplexed.
Buffers are re-used for both data transfer directions.
III. Functional Operation
A. Interfaces
This chip will only respond to Type 0 configuration cycles.
IV. Signal Descriptions
A. Interfaces
1. PCI Bus
There are 49 signals on the PCI interface. This includes the
minimum 45 for a slave, as well as two (2) for arbitration by a
master (req_, gnt_), and two (2) for error reporting (perr_,
serr_).
The optional lock (lock_) signal is not supported. Apple
discourages its use. The PowerPC does not generate locked
accesses to PCI busses.
One interrupt output signal is supported, nominally as INTA#,
however it may be wired to any of the four lines.
PERR# and SERR# are fully implemented; however, the host system
chip sets presently in use do not use them.
Power Macintoshes maintain cache coherency only within main
system memory and do not generate SDONE or SBO# cache support
signals, which remain permanenetly pulled up by resistors.
V. Testability
A pad ring NAND logic chain is incorporated into the device. This
supports two functions. First, it provides a simple way to generate
the input threshold tests for chip test. Second, it facilitates a
form of in circuit testing where connection of the net to the pin
can be verified by observing a single output pin.
VI. Verification
A. Design
1. Simulation
The simulation environment was created to look like the system
block diagram above (section I.C. System).
2. Environment
Verilog HDL was used for design and simulation. Signalscan was
used for simulation analysis. Synopsys was used for conversion
of the high level design to gate level.
B. Component Testing
The test pattern for component test was extracted from the simulation
environment by adding a block to capture all of the data and
direction control information at the chip pins drivers. This
included the direction control information as well as when the
output data was sampled after turnaround. This collected information
was then transformed into appropriate test pattern files and test
control files for the semiconductor manufacturer to test the
fabricated chips. Additional patterns for use only at chip test for
NAND ring parametric tests were also written.
C. Coverage Analysis
The test patterns attempt to provide full fault detection coverage.
Full march patterns are run through each of the buffers and through
the entire configuration register set. All address or count
comparison circuits are tested for all combinations at each bit
position with that position critical.
Our silicon vendor provided a check of toggle coverage at 99.5%. Our
own anaysis of the nodes not toggled showed that no more could be
toggled.
VII. Purchased Technology
CMOS 0.7u 5V
Gate Array 26,000 usable gates
VIII. References
Documents
+PCI Local Bus Specification, Revision 2.0, April 30, 1993, (c)
1992, 1993 PCI SIG
+PCI System Design Guide, Revision 1.0, September 8, 1993, (c)
1993 PCI SIG
+PCI BIOS ROM Specification, Revision 2.0, July 20, 1993, (c)
PCI SIG
+PCI to PCI Bridge Architecture Specification, Revision 1.0,
April 5, 1994, PCI SIG
+Designing PCI Cards and Drivers for Power Macintosh Computers,
Draft August 3, 1994, (c) 1994 Apple, Addison Wesley
+Designing Cards and Drivers for the Macintosh Family, Third
Edition, (c) 1992 Apple, Addison Wesley
+Guide to Macintosh Family Hardware, Second Edition, (c)1990
Apple, Addison Wesley
+Macintosh Developer Note Number 8, APDA
+Standard for a Simple 32-Bit Backplane bus: NuBus, ANSI/IEEE
Std 1196-1987
+Standard for a Simple 32-Bit Backplane bus: NuBus, ANSI/IEEE
Std 1196-1990
+1275-1994 Standard for Boot (Initialization, Configuration)
Firmware, IEEE part number DS02683
Machines Affected: PowerWave