Burst-mode Memory Access
------------------------
The Macintosh IIfx, like the Macintosh IIci, supports burst-mode memory
access. However, the Macintosh IIfx support burst access for reads and
Page Mode Writes, while the IIci only supported burst reads. The FMC gives
the Macintosh IIfx the ability to support burst-mode access. This enables
the CPU to read and write groups of data in fewer clock cycles.
On the Macintosh IIfx, burst-mode reads are only done when the data is
not located in the internal 256 byte and 32K Static RAM Cache. When the
Macintosh IIfx reads from memory, the first access takes 6 clock cycles.
The next 3 reads are performed at 3 clock cycles each. This is referred
to as "6 3 3 3 burst reads."
Burst-mode access must be supported by the RAM as well as the memory
controller. When memory is accessed, we use RAS (Row Address Selection)
before CAS (Column Address Selection) to address the chip. We select the
row of data we wish to access with a RAS, then assert the CAS lines to
select the correct data column. It takes about 3 clock cycles for the
chip to select RAS and 3 more cycles to address CAS before the data is
ready to read or write.
When burst-mode is enabled, the RAS lines are held high until the burst
cycle is over. The memory controller only has to change the column
address (CAS) line to access the next bit of data in that row. It
continues to change the CAS line until the burst cycle is over. Because
the system does not have to readdress the RAS line, 3 cycles each
read/write, it saves 9 clock cycles.
Page Mode Write
---------------
A Page Mode Write is similar to a burst-mode read. When data is written
out, the system uses Latch Writes for the first write. If the instruction
is also a write and the address is within the same page of memory as the
previous write, Page Mode Write is used. Page Mode Writes keep the RAS
line held high in the save "page" of memory.